1. Field of Invention
This invention relates generally to semiconductor memories and specifically to content addressable memories.
2. Description of Related Art
A CAM includes an array of memory cells arranged in a matrix of rows and columns. Each memory cell stores a single bit of digital information, i.e., either logic zero or logic one. The bits stored within a row of memory cells constitute a CAM word. During compare operations, a comparand word is received at appropriate input terminals of the CAM and then compared with all the CAM words. For each CAM word that matches the comparand word, a corresponding match line signal is asserted to indicate a match condition. When there is a match condition, the index or address of the matching CAM word is read from the CAM. Associative information stored in, for instance, an associated RAM, may also be provided.
FIG. 1 shows a typical CAM row 1 as having n CAM cells 10(1)-10(n) each coupled to an associated match line ML. A pull-up transistor 12, coupled between a supply voltage V.sub.DD and match line ML, has a gate tied to ground potential, and therefore remains in a conductive state. Prior to each compare operation between an n-bit comparand word and an n-bit CAM word stored in CAM cells 10(1)-10(n), match line ML is pre-charged to supply voltage VDD via pull-up transistor 12. The n-bits of the comparand word are compared with corresponding bits of the CAM word in respective CAM cells 10(1)-10(n). If all bits of the comparand word match corresponding bits of the CAM word, the match line ML remains charged to indicate a match condition. Conversely, if one of the comparand bits does not match the corresponding CAM bit, the CAM cell 10 storing that CAM bit discharges match line ML toward ground potential to indicate a mismatch condition.
As described above, the match lines in a CAM array are typically pre-charged to the supply voltage VDD for each and every compare operation. Thus, for each mismatch condition, an associated match line ML is first charged toward V.sub.DD and then discharged toward ground potential. Current flow associated with this charging and discharging results in undesirable power consumption. Further, as the number of CAM cells in each row of a CAM array increases, capacitive loading on the match lines increases accordingly. As loading on the match lines increases, the current required to charge the match lines toward the supply voltage increases. Accordingly, as CAM words are widened, for example, to accommodate longer Internet addresses, power consumption resulting from charging the match lines during compare operations may significantly increase. Therefore, as CAM words become wider, it is desirable to reduce power consumption during compare operations.